| 100Mhz
& 128K Memory |
For general
purpose logic analysis, configure LG480 to 25Mhz on all
48 channels or 100Mhz for high speed critical applications.
If debugging of your application requires very large memory,
LG480 offers you 128K memory as standard. But don't waste
time for waiting until these large amount of data is displayed
if you don't need it. Just reduce the memory depth with
a mouse click and save time. |
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| Easy
to Use Interface |
LG480 operates
under Microsoft Windows™ 95/98 or Windows NT/2000/XP.
All datat and setup displays offer an intutive setting
of parameters and powerful data analysis. |
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| Reconfigurable
Design Board |
| A univdersal
FPGA/CPLD development breadboard is supplied as an integral
part of LG480 to verify system design, adopting a 'burn
& learn' verification methodology. The onboard JTAG
port connects to user PC to download designs. A variety
of connectors and peripherals offers maximum flexibility. |
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| Configure
the System to meet Your Needs |
 |
| To meet the
needs of your design, configure LG480 as 48 channel Logic
Analyzer, or as 48 channels of PatternGenerator, or a
combination of Logic Analyzer & Pattern Generator.
|
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| SOC
Adapter |
The SOC adaption
is a simple way of analyzing internal nodes in FPGAs or
ASICSs.
By integration of a Logic Analyzer, Pattern Generator
and a scanner module, up to 1024 channels dcan be traced
inside a silicon system.
The SOC adaption is scalable up to 32 multiplexed signals. |
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| 48 Channels
of Logic Analysis |
The LG480
features 48 channels of Logic analysis with disassembly
support for most popular 8 bit and 16 bit embedded controllers
with 128K deep trace buffer.
All debugging and trace information can be displayed at
assembler level, numeric, waveform or as ‘C’
trace. A unique single probe connection allows collection’s
in State or Timing mode. |
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| 48 Channels
of Pattern Generation |
The LG480
Pattern generator provides 48 fully programmable data
stimulus for active testing of your system.
Pattern data can be easily generated by either directly
importing Logic Analyzer traces or by using a variety
of built in Pattern generation menu options.
Simulator Outputs in ASCII format may also be imported. |
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| Reduce
Learning Time |
| The Trigger
Sequence dialog box defines the sequence of occur-rence
of the defined trigger events. Up to 4 levels of Trigger
sequence can be programmed in an easy to understand If…then…
ButIf... Format. An 64K event counter/ delay is also available.
|
| |
| Symbolic
Debugging |
| A variety
of Symbol convreors is available including a standard
LG480 format. The number of Symbols is unlimited. The
Trigger Word Dialog Box includes a Sumbol browser for
comfortable Symbolic Triggering.Convertor for Xilinx is
also included to facilitate mapping and selection of physical
channels. |
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| Trigger
on a Source Code Line |
| To make debugging
even more comfortable, the HLL-Manager has a built-in
Trigger window.This trigger window allows setting Trigger
Points to a specific Source Code Line. No moer manual
Trigger SetUps are required. After loading a suitable
Setup, the Triggerword is set directly to the Source Code
Line and a recording is started. |
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| Powerful
Triggering Sequence |
| |
 |
The squence
dialog box defines the sequence of occurrence of the trigger
events defined in the Trigger Dialog Box. Up to 4 levels
of Trigger sequence can be programmed in an easy to understand
If...then...ButtIf...Format. A 64K event counter/delayfor
the first level of Trigger sequence. |
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| Waveform
View |
| |
 |
This screen
shows up to 32 channels and lets you assign names to physical
channel, rename signals and group signals into busses.
The window also lets you zoom in on an area of interest.
Markers and Cursors are provided to show the value at
the specific time location. |
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| Numeric
View |
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 |
In this view,
the channels are grouped and displayed as numeric values
namely hex, decimal, octal and binary. |
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| Poweful
Disassemblers |
 |
| LG480 Disassemblers
support most of today's 8/16 Embedded Control and High
Performance Micro Processor families. All Disassemblers
are developed to meet the requirements of the "Flexible
Adaption Concept" and to generate as much information
as possible. Pipelined processor activity and non-executed
instructions as well as jumops are detected and marked
in the disassembler listing. The SOC-Disassembly Pod can
also be effectively used to capture real time timing waveforms. |
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| High Level
Language Debugging |
 |
The High Level
Language manager correletaes rec orded procedure data
to High Level Source Code. The HLL Manager is am independent
Windows program and communicates with the Logic Analyzer
unsing the software interface of the system. Setting the
cursor to a recorded processor address in one of the data
views like Timing, List or Disassembler causes the HLL-Manager
to displaythe corresponding Source Code Line.
This new technology enables engineers to view broad-level
design and then debug an entire digital system - i8ncluding
embedded microprocessor cores and the software that runs
on them - into an FPGA/CPLD. |
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| Pattern
Generator |
| As the compexlity
of digital circuits increarses continuously, the cost
of device testing has also increased sharply. The increasing
complexity of testing has shifted more and more of the
testing responsibility towards the design engineers. LG480
with biult in Pattern genetator and Analyzer forms a virtual
ATE system. The user prototype of the system accepts simulationoutput
and generates commands to configure the pattern generator
and logic analyzer. The DUT (Device Under Test) receives
stimilus from the pattern generator and generates output
response to the Logic Analyzer. The actual response captured
by the Logic Analyzer can be fed into simulation software
for further processing.The simulation system vcan display
a graphical comparison of the expected output waveforms
(from the simulation) and the actual waveforms from logic
analyzer. |
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| Features: |
- 48 Channels x 128K Real Time Logic Analyzer
- 48 Channels x 128K Real Time Pattern Generator
- Pattern Waveform Editor
- Ready to use Standard Patterns like Counters,
Clocks etc.
- Supports Xilinx WebPack / Foundation Software.
- Multiple display cursor with real time readout.
- Color Coded signals and probes.
- Multiple reference buffer 40X128K
- Display state data in Hex, Binary, Octal,
Decimal.
- Color Coded signals and probes
- Sixteen 48-bit Trigger Word with 65535 delay/event
counter.
- 4 level Trigger with IF-THEN-BUTIF seuuencing.
- 16 Trigger Delay modes.
- Export data to popular Spreadsheets &
Word processor.
- 8 bit Disassembler support for 8085, Z80,
6502, 6809, MCS51
- 16 bit Disassembler support for 8088, 8086,
68000, 68010
- SOC Adsaptor support for embedded CPU core.
- CPLD/FPGA Trainer Board with JTAG Programmer
and cables.
|
| |
| LG480 |
Logic
Analyzer |
Pattern
Generator |
|
Channels
Memory
Speed
Trigger Sequence
Event/Delay
Disassembler |
48
128K
upto 100Mhz
4 Level
65535
8/16 bit |
48
128K
upto 50Mhz
N.A
N.A
N.A |
|
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| SOC Adaptors |
| |
| The adapterfor
SOC Trace enables trace of internal signals in FPGA and
ASIC devices. The trace data are sampled inside the chip
and send-out on multiplexed channels. The multiplexer
is controlled by LG480. If all channels are inside one
32 bit block, the logic analysis can run at full speed.
If signals out of two groups is to be sampled at the same
time, the sample rate is halved. Maximum of 1024 characters
can be traced by the scanner mode. The scanner module
has upto 1024 signal inputs for customer usage, 2 contrrol
lines for programming, one clock input for the scanner
clock, one reference clock output, a synchronization signaland
uptp 32 multiplexed trace signals. The scanner module
can be written in VHDL/ABEL. Signals of an embedded processor
core can also be traced. |
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